The present invention relates to a flash memory system which is used for a flash memory card having a flash memory as a storage device, and/or an external memory device having a flash memory as a storage medium. When it is used an an external memory device, it operates as if a hard disc device or a floppy disc device in a computer system.
A flash memory system comprises at least a support card, one or plurality of flash memory chips mounted on said card, and a flash memory controller mounted on said chip for controlling operation of said flash memory chips. A flash memory chip is sometimes called an EEPROM, or electrically erasable programmed read only memory.
FIG. 3 shows a block diagram of a prior flash memory controller. In FIG. 3, the numeral 1 is a host computer, 2 is a flash memory controller, 3 is a buffer memory implemented for instance by an S-RAM, 4 is a flash memory chip, 6 is a buffer memory manager, 7 is a flash memory format control, 8 is a host-bus multiplexer, 9 is a buffer memory multiplexer, 10 is a flash memory sequencer, and 12 is an ECC process circuit which functions to process an error of data during transfer between a host computer and a flash memory chip.
(1) Flash Memory Controller
Conventionally, a flash memory card which has a flash memory as a storage device, and an external memory device having a flash memory as a storage medium have been known. The flash memory card, and/or the external memory device has a flash memory controller for controlling a flash memory chip.
A flash memory controller functions to control write/read operation to/from a flash memory based upon a command by a host computer. The flash memory controller controls to write/read a flash memory, by carrying out a transfer control of data, like a hard disk controller.
A flash memory controller has an external buffer memory, through which a write/read operation to/from a flash memory is carried out.
When data is written in a flash memory, the control is as follows. First, data transferred from a host computer is stored in a buffer memory. Then, the data stored in the buffer memory is read out, and after the format process is carried out, the data is transferred to the flash memory. Thus, the write operation into a flash memory is accomplished (the data transfer is carried out through the similar path to that of a hard disk controller).
(2) Prior Flash Memory Controller
As shown in FIG. 3, a flash memory controller 2 is coupled with an external buffer memory 3 and a flash memory 4, and said flash memory controller 2 is coupled with a host computer 1 (which is for instance a personal computer).
A flash memory controller 2 has a host interface control 5, a buffer memory manager 6, and a flash memory format control 7.
The host interface control 5 has a host-bus multiplexer 8, the buffer memroy manager 6 has a buffer memory multiplexer 9, and the flash memory format control 7 has a flash memory sequencer 10 and an ECC process circuit 12 for error process.
Said host interface control 5 sends/receives a control signal for data transfer to/from a host computer 1, so that the host-bus multiplexer 8 operates on time division basis for conversion of a data bus of 16 bits in a host computer 1 to a data bus of 8 bits (which is called a primary bus) in a flash memory controller 2.
Said flash memory format control 7 sends/receives a control signal for data transfer to/from a flash memory 4. In that case, the flash memory sequencer 10 controls an access process to write and/or read the flash memory 4. The flash memory format control 7 carries out the data transfer between the flash memory 4 which has 8 bits data terminal and the 8 bits bus (which is called a secondary bus) in the flash memory controller 2.
Said buffer memory manager 6 switches said primary bus and said secondary bus on time division basis so that one of those buses is coupled with the buffer memory 3.
(3) Operation of a Flash Memory Controller
As described above, a flash memory controller 2 has an external buffer memory 3, as is the case of a hard disk controller, so that the data transfer between a host computer and a flash memory is carried out through said buffer memory.
The data stream is classified to two cases according to data transfer rate.
The first data stream is a stream in a primary bus one end of which is coupled with a host computer, and therefore, the first data stream has data transfer rate which is equal to that of a host computer.
The second data stream is a stream in a secondary bus one end of which is coupled with a flash memory 4, and therefore, the second data stream has data transfer rate which is equal to that of a flash memory 4.
As the transfer rate to a flash memory is slower than that of a host computer, the transfer rate in a secondary bus is slower than the transfer rate in a primary bus. Further, when data is written in a flash memory, a bus is occupied for sending a command and an address to the flash memory, and receiving a status out of the flash memory, and some busy condition of a bus exist to write/read/erase a flash memory for informing an inner condition of the flash memory to the flash memory controller. The data transfer rate must be slow in a flash memory because of above operations.
Said buffer memory 3 is located between two means having the different transfer rate with each other for buffer operation. A plurality sectors data from a host computer is received by said buffer memory simultaneously, therefore, a through-put is apparently increased.
However, a prior flash memory controller has the disadvantages as follows.
(1) A prior flash memory controller has advantage that a through-put is increased as it has an external buffer memory which receives a plurality of sectors from a host computer simultaneously. However, if the capacity of the buffer memory is small, the effect of above is small.
Further, when a host computer issues a write command, data from a host computer is stored temporarily in a buffer memory, and then, the buffer memory is read out so that the data thus read out is transferred to a flash memory. So, it takes some time to write data in a buffer memory and read data out of the buffer memory.
Further, data occupies a buffer memory twice as long as an access time, as two cycles (write cycle and read cycle) are necessary. Therefore, write time to a flash memory must be essentially long.
(2) Conventionally, a host bus multiplexer 8 converts 16 bits parallel data from a host computer to 8 bits parallel data to a primary bus.
Therefore, the transfer rate to a primary bus must be twice as quick as that of a host computer. The operational rate of a buffer memory manager and a write operation of a flash memory must also be twice as quick as that of a host computer. Further, it is requested that an error correction means in a flash memory format control has a priority to interrupt to access a buffer memory.
Thus, a buffer memory is accessed frequently, by an error correction means, a host interface control (lower bit access and higher bit access), a write access to a flash memory, et al. Those accesses to a buffer memory operates on time divisional basis.
A flash memory controller must operate several times as fast as a buffer memory, because of said time divisional operation.
For instance, when a buffer memory is a static RAM with access time 100 nS, the access time to a host computer must be slower than 500 nS. Therefore, an access rate to a flash memory in a prior art is slow.
(3) If we wish to have a fast device for writing/reading data, we must have not only a flash memory with high speed operation, but also a buffer memory with a cash memory with large capacity and short access time.
However, a commercial cash memory with high speed operation has only small capacity, and high cost. Further, as power consumption of the same is high, it is not useful in many situations.